Design of a Soft-core Processor Based on Opencores with Enhanced Processing for Embedded Applications

Soft-core processors are being increasingly used in various embedded applications due to their flexibility, cost effectiveness and platform independence. It enables designers to modify the core designs with ease to achieve specific application goals. In this paper, the design of an enhanced soft-core processor based on OpenCores that is suited for telecommunication, multimedia and a variety of embedded applications is presented. The OR1200 platform, which is a 32-bit DSP, with RISC Harvard micro architecture including a 5-stage integer execution pipeline, is used. We enhance the processor design to include a Global Memory Stall Controller which manages the Data Path Unit of the processor and distributes stall signals whenever the memory latency cannot be hidden. Also, we suggest improvements in the data path of the processor to enhance it for better multimedia applications. Finally, we propose to add a Hazard Controller to the execution pipeline to handle data and branch hazard.